Google Puts Every AI Agent in Its Own microVM

Google introduced Agent Compute Engine on 22 October, a runtime that gives every AI agent its own hardware-isolated microVM with persistent Hyperdisk storage for workspace and context. Preview access is promised in the coming months; Google says its pause and resume path completes in under 500 milliseconds across a fleet of 200,000 agents.

The design separates two things that agent platforms previously merged: identity and execution state. Each agent receives its own identity, and credentials are handled outside the microVM so raw secrets do not sit inside the process that runs model-generated code. Because the workspace persists, operators must now decide which files survive a session, who can read them and how they are removed afterwards.

Google also described Agent Substrate, an open-source runtime for Kubernetes deployments on Google Kubernetes Engine, aimed at teams that want to control the execution layer themselves. The announcement is a roadmap document rather than a shipping product: preview access has not opened, and an announced runtime should not be treated as a deployable option until the interfaces and terms are published.

For hardware planning, the architecture matters more than the branding. A model that runs one agent per microVM changes the ratio of compute to memory and storage: many small virtual machines with modest vCPU counts, private memory, a persistent virtual disk and an isolated network path. Density, boot time and per-agent storage become the sizing variables instead of peak accelerator throughput.

That pulls demand toward different components than a GPU cluster does. Expect heavier consumption of server CPUs, DDR5 RDIMMs, NVMe boot devices, TPM or secure-element silicon for identity, 25G or 100G network interfaces and out-of-band management controllers. It also raises the value of hardware root of trust, because agent identity anchored in firmware is harder to spoof than a token stored in a container.

Buyers specifying agent infrastructure should size for concurrency and cold-start latency, not for training throughput, and should confirm that their platform's isolation claims have been independently reviewed. Our catalogue lists interface and security-adjacent parts for these builds, including the RTL8211F gigabit PHY and the CH32V307 RISC-V MCU used in board management and instrumentation designs.